Conventional locking detection circuit for CDR (Clock Data Recovery) circuits has two types according to two implementation ways of CDR circuit.
One is for analog CDR circuits based on PLL (Phase Locked Loop), which determines a threshold by utilizing two reference voltages and two comparators, and considers the analog CDR circuit to be locked if a control voltage of a VCO (Voltage Controlled Oscillator) in the CDR circuit is within the threshold and is unvaried for a predetermined period, contrariwise, to be unlocked. Such a locking detection circuit has following restrictions however. First, it's necessary to use simulation comparators with high accuracy and high sensitivity, which may consume size and power of the locking detection circuit. Second, after the CDR circuit is locked, the control voltage of the VCO is an analog signal, but it's hard to determine a turn threshold of the control voltage due to manufacturing process variation. Third, in the event that data signals outputted by the CDR circuit include spread spectrum data, this locking detection will be failed if the control voltage of the VCO is drifted as the spread spectrum and beyond the thresholds of the comparator.
Another is for digital CDR circuits based on phase interpolation digital filter, which outputs phase detection results including up or dn by a bang-bang Phase detector, and then performs digital filtering and counting to the phase detection results. The digital CDR circuit will be considered to be locked (namely the rising edges of the clock pulses and the data signals are aligned) if the total amount of the result of up approaches or is the same with that of the total amount of the result of dn, contrariwise, to be unlocked. Such a locking detection circuit has the following restrictions however. First, when a data rate of the data signal outputted by the CDR circuit reaches to 1 Gbps or over, this locking detection circuit will appear tight time sequence, which desires a larger size and larger power accordingly. Second, in the event that data signals outputted by the CDR circuit include spread spectrum data, it's necessary to be informed in advance that if the outputted data signals pertain to upward spread spectrum or downward spread spectrum, and the spectral distribution of the data signals, so that parameters could be determined to perform locking detection for the CDR circuit; otherwise, this locking detection will be failed.
Both of the foresaid locking detection circuits for CDR circuit are based on a specific CDR circuit, and the implementations of locking detection for CDR circuits are depended on a specific CDR circuit, which limits its application scope. Therefore, there is a need for an improved locking detection circuit for CDR circuits to overcome the above-mentioned drawbacks.